The present invention relates to a median filter, and more particularly, to a median filter capable of providing easier implementation and a simplified change of the degree.
A median filter is a non-linear filter for outputting a value of a middle size with regard to a predetermined data sequence. Among N+1 data applied to the median filter, a middle value is larger than or equal to N/2 data, or less than or equal to N/2 data, in which N is an even number and represents the degree of the median filter.
Figs. 1A and 1B are views for explaining characteristics of a median filter. FIG. 1A shows an example that a two-dimensional image is filtered using a median filter of 3 by 3. In Fig. 1A, a binary value of "100" is an impulse noise with respect to neighboring values of "1". A pixel value in which impulse noise occurs is replaced by a middle value among the pixel value and neighboring values by using the median filter. Such a median filter effectively removes the impulse noise. A linear filter which averages input values of the linear filter can deteriorate the boundary portion of an image. However, by using a median filter, a boundary characteristic of an image is maintained as shown in Fig. 1B. The median filter having such a characteristic is widely used in image signal processing for television or medical equipment.
The median filter is implemented via methods of using software and hardware. A method of using software uses a predetermined sorting algorithm in a general-purpose microprocessor or digital signal processor (DSP) to sort data sequence and then obtain data having the middle value among the sorted data sequence. However, this method has a drawback that can not process data in a real time since data processing slows down. In order to speed up data processing, studies for implementing a median filter in hardware such as ASIC or FPGA have been developed. The prior art for implementing the median filter in hardware is disclosed in U.S. Pat. No. 5,138,567. FIG. 2 shows a median filter proposed in the prior art, particularly a four-degree median filter. In FIG. 2, four values I.sub.1 .about.I.sub.4 input in sequence are delayed via delays 22.sub.1 .about.22.sub.4 by a predetermined time. A following input value I.sub.5 input to a first delay 22.sub.1 and adders 21.sub.1 .about.21.sub.4.The adders 21.sub.1 .about.21.sub.4 individually calculate values between the input value I.sub.5 and the output values of the delays 22.sub.1 .about.22.sub.4, and the calculated values are stored in shift registers 23.sub.1 .about.23.sub.3, respectively. Values stored in the shift registers 23.sub.1 .about.23.sub.3 are output to a selection unit 24. The selection unit 24 judges magnitudes of the output values from the shift registers 23.sub.1 .about.23.sub.3, and supplies the judged results to a multiplexer 25 as a selection control signal. A multiplexer 25 outputs a middle value OUT among the output values of the delays 22.sub.1 .about.22.sub.4 according to the selection control signal received from the selection unit 24. In the case where a median filter is implemented in hardware, it is advantageous to adopt a small number of gates in view of costs and the degree of integration. However, the selection unit in FIG. 2 is embodied to a comparison logic for comparing a magnitude of the output values from the shift registers. The comparison logic should be re-designed when the degree of the filter is changed, and specially there has difficulty in design since the higher degrees are, the more complicated logic is.